1. Field of the Invention
The present invention relates to the method of fabrication of diffusion self-aligned, short channel MOS devices, including a method for simultaneous fabrication of depletion MOS devices and low body effect MOS devices, and further relates to diffusion self-aligned, short channel devices resulting from such method.
2. Discussion of the Prior Art
High gain, high speed diffusion self-aligned, short channel MOS devices may be fabricated by ion implanting a heavily doped p-type region within a lightly doped p-type substrate. One of the n-type active diffusion regions is then disposed within the p-type impurity region or well. By this means the effective channel width of a MOSFET may be accurately controlled according to the extent of the p-type impurity region below the gate electrode. Examples of this type of device are disclosed in Gauge et al, U.S. Pat. No. 3,909,320 and U.S. Pat. No. 3,845,495. While the diffusion self-aligned MOS transistor has a higher gain factor than the standard MOS device, it is possible to substantially increase the gain factor of a diffusion self-aligned MOS device by the improvements disclosed below. Furthermore, where a diffusion self-aligned MOS transistor has been combined in integrated circuitry with a depletion device, the prior art has found it necessary to follow the fabrication of a standard MOSFET with a channel implantation in order to obtain acceptable circuit speeds. An example of this necessity is illustrated in the prior art in Ohta et al, "A High-Speed Logic LSI Using Diffusion Self-Aligned Enhancement Depletion MOS IC," IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 5, pp. 315, 317 (October 1975). The prior art channel implantation step, used to decrease the propagation delay time of an inverter circuit, results in a method of fabrication which increases the complexity and difficulty of fabrication by introducing one or more additional masking steps. Moreover, the efficiency of the diffusion self-aligned device in the inverter circuit may easily be affected by the subsequent ion implantation step.
What is needed, then, is a means for improving the performance of a diffusion self-aligned, short channel device in such a manner that the complexity and difficulty of its method of fabrication is not increased and such that accompanying depletion MOS devices and low body effect MOS devices may be easily and simultaneously fabricated on the same integrated circuit chip.